Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal Processing

Author

Gatet, L. ; Tap-Beteille, H. ; Lescure, M.

Author_Institution

Electron. Lab., Toulouse

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

922

Lastpage

925

Abstract

The feedforward multi-layer perceptron (MLP) type neural network (NN) presented in this paper has been developed for on-board applications of high-speed signal processing (240 MHz). It is fully analog in order to avoid analog-digital conversions and to limit chip size and power consumption. It is constituted by a single input, ten neurons in the hidden layer and a single output. The MLP-NN has been implemented in a 84 pins -0.6mum CMOS ASIC. The NN layout size is 1.8mmx0.7mm and the consumption is intended less than 600mW. This paper presents the design and simulations of each implemented cell and the first experimental tests achieved on the implemented ASIC.

Keywords

CMOS analogue integrated circuits; application specific integrated circuits; integrated circuit design; integrated circuit testing; multilayer perceptrons; signal processing; CMOS ASIC; CMOS MLP analog neural network; analog-digital conversions; chip size; fast on-board signal processing; feedforward multilayer perceptron type neural network; frequency 240 MHz; power consumption; size 0.6 mum; size 0.7 mm; size 1.8 mm; Application specific integrated circuits; CMOS process; Energy consumption; Feedforward neural networks; Multi-layer neural network; Multilayer perceptrons; Neural networks; Signal design; Signal processing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379940

Filename

4263518