• DocumentCode
    2961325
  • Title

    Using FPGAs to Implement Artificial Neural Networks

  • Author

    Granado, J.M. ; Vega, M.A. ; Pérez, R. ; Sánchez, J.M. ; Gómez, J.A.

  • Author_Institution
    Extremadura Univ., Caceres
  • fYear
    2006
  • fDate
    10-13 Dec. 2006
  • Firstpage
    934
  • Lastpage
    937
  • Abstract
    In this paper we show and analyse the different alternatives used to implement, until now, artificial neural networks in FPGAs. At the moment, this is a very active research field, and still, there is a long way to travel. In this work, we focus on important aspects like: the neuron´s multiplier and activation function implementation, the storage and representation of the implicated data, the most habitual improvements and simplifications, the reconfigurable hardware systems used to implement artificial neural networks,... Ending this paper with the conclusions obtained from this analysis work. Among them, it is important to highlight that the use of FPGAs to implement ANN is not only feasible, but also presents a hopeful future.
  • Keywords
    field programmable gate arrays; neural chips; FPGA; artificial neural networks; neuron multiplier function; Artificial neural networks; Data processing; Field programmable gate arrays; Neural network hardware; Neural networks; Neurons; Parallel processing; Parallel programming; Signal resolution; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
  • Conference_Location
    Nice
  • Print_ISBN
    1-4244-0395-2
  • Electronic_ISBN
    1-4244-0395-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2006.379943
  • Filename
    4263521