A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology

Author

Thuries, Stéphane ; Tournier, Éric ; Graffeuil, Jaques

Author_Institution

Paul Sabatier Univ., Toulouse

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

991

Lastpage

994

Abstract

A 3 bits - 0.25 μm BiCMOS SiGe:C accumulator operating up to 15 GHz clock frequency is presented. It is based on a high-speed and low-power three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop latch-up register. With this technique, the dissipated power is reduced by 30% over the usual four-levels series logic. The circuit integrates 203 (without buffers, 230 with) transistors and dissipates 67 mW (without buffers, 119 with) from a 2.7 V supply.

Keywords

BiCMOS logic circuits; Ge-Si alloys; MMIC; direct digital synthesis; flip-flops; low-power electronics; BiCMOS SiGe:C technology; D-flip-flop latch-up register; DDS; clock frequency; direct digital synthesizer; frequency 15 GHz; full-adder; phase accumulator; power 67 mW; size 0.25 μm; voltage 2.7 V; word length 3 bit; BiCMOS integrated circuits; Bipolar transistors; Clocks; Energy consumption; Frequency; Laboratories; Logic; Registers; Signal resolution; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0394-4

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379957

Filename

4263535