Development of a high performance TSPC library for implementation of large digital building blocks

Author

Le Chapelain, Bertrand ; Mechain, Alexandre ; Savaria, Yvon ; Bois, Guy

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada

Volume

1

fYear

1999

fDate

36342

Firstpage

443

Abstract

In this paper, we present a heuristic study of split-output latches built according to the true single-phase clocked circuits (TSPC) design style. Previous studies have shown that TSPC circuits can operate at very high frequencies. Our goal is to implement large digital building blocks operating at 1 GHz or more (in 0.35 “m CMOS technology). Our methodology started with the development of a first set of cells based on ad-hoc design. A fast semi automatic method was then developed to reduce the number of simulations. Based on the experience acquired with TSPC optimization, we proposed an automatic algorithm to optimize TSPC cells and a method to realize libraries of logical standard cells. This paper describes the different steps followed to elaborate the TSPC library. The method and the cell library are validated by characterizing small digital building blocks

Keywords

CMOS logic circuits; cellular arrays; clocks; flip-flops; logic CAD; software libraries; 0.35 micron; 1 GHz; CMOS logic; ad-hoc design; digital building blocks; heuristic study; high performance TSPC library; logical standard cells; semi automatic method; split-output latches; true single-phase clocked circuits; CMOS technology; Circuit synthesis; Circuit testing; Clocks; Frequency; Inverters; Latches; Optimization methods; Software libraries; VHF circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777908

Filename

777908