4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS

A 4-Gb/s, low-power, 2³¹-1 output length, pseudo random binary sequence (PRBS) generator with a wave-pipeline technique is presented. A thirty-one stages linear feedback shift register (LFSR), whose feedback taps are connected to the first stage through EXOR, is adopted. In this LFSR, each stage consists of D-FF employing a true single phase clock (TSPC) type to increase the operating frequency. In the conventional design, to obtain correct output from feedback loop under high-speed operation, the propagation delay of the critical path containing D-FF and EXOR must be less than one shifting clock period. The proposed wave-pipeline technique bypasses the portion of feedback loop, and thereby relaxes the restriction of this path up to two shifting clock periods. Applying this method, the delay of critical path can be reduced to D-FF´s one. As a result of this improvement, the proposed generator operates at 48% higher frequency than the conventional one. Besides the performance enhancement, this generator occupies small area and consumes low power because of employing standard CMOS logic. Therefore, the proposed circuit can be implemented in system on chip (SoC) and perform an accelerated error test as a part of built-in self tester (BIST) for the serial link based on standard static CMOS logic. This circuit was simulated in a 0.18-μm 1P5M CMOS process. The total power dissipation at 4-Gb/s and 1.8-V supply voltage is 9.5 mW and the active area is 0.004 mm².