DSP power reduction through Generalized Carry-Save arithmetic

Author

Pan, Chiu-Wei ; Song, Yuanchen ; Wang, Zhao ; Sechen, Carl

Author_Institution

Electr. Eng. Dept., Univ. of Texas at Dallas, Richardson, TX, USA

fYear

2009

fDate

4-5 Oct. 2009

Firstpage

1

Lastpage

4

Abstract

We present a new method to systematically parallelize networks of additions and multiplications to dramatically reduce power dissipation in digital signal processing (DSP) blocks. This new method is termed Generalized Carry-Save (GCS) arithmetic. Results are presented for three industrial DSP blocks, separately implemented in IBM 130 nm, TI 65 nm and TI 45 nm technologies. Compared with the best delays obtainable using the best scripts from the leading commercial synthesis tool, GCS produces DSP block implementations that are at least 30% and up to 2X faster for similar area. As a consequence, the power supply voltage can be reduced to realize quadratic power savings for the same delays.

Keywords

carry logic; digital signal processing chips; power electronics; DSP power reduction; digital signal processing block; generalized carry-save arithmetic; power dissipation; power supply voltage; quadratic power savings; Adders; Compressors; Delay; Digital arithmetic; Digital filters; Digital signal processing; Energy consumption; Power dissipation; Signal synthesis; Vectors; DSP networks; Generalized carry-save arithmetic; networks of additions and multiplications;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems Workshop,(DCAS), 2009 IEEE Dallas

Conference_Location

Richardson, TX

Print_ISBN

978-1-4244-5483-9

Electronic_ISBN

978-1-4244-5484-6

Type

conf

DOI

10.1109/DCAS.2009.5505725

Filename

5505725