Title :
A sophisticated bit-by-bit verifying scheme for NAND EEPROMs
Author :
Sakui, K. ; Kanda, K. ; Nakamura, H. ; Imamiya, K. ; Miyamoto, J.
Author_Institution :
ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
A sophisticated bit-by-bit verifying scheme, which is able to realize a tight programmed threshold voltage distribution of 0.8 V, has been proposed for NAND EEPROMs. A new bit-by-bit verifying circuit is composed of a conventional sense amplifier and a dynamic latch circuit with only three transistors, increasing the chip size of the 64 Mbit NAND EEPROM less than 1%.
Keywords :
EPROM; NAND circuits; integrated memory circuits; 0.8 V; 64 Mbit; NAND EEPROM; bit-by-bit verifying scheme; dynamic latch circuit; programmed threshold voltage distribution; sense amplifier; Buffer storage; Circuits; Dynamic programming; EPROM; Laboratories; Latches; Power supplies; Threshold voltage; Ultra large scale integration; Variable structure systems;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688098
