M-array VLSI architecture for order statistic filters

Author

Lin, Ching C. ; Kuo, Chung J.

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

Volume

6

fYear

1996

fDate

7-10 May 1996

Firstpage

3264

Abstract

The order statistic filter is an important nonlinear filter for many image processing applications. We propose several simplified algorithms for the VLSI implementation of an order statistic filter. Specifically, we propose: (1) a simplified algorithm to reduce the chip area of an order statistic filter; (2) a simplified algorithm using fewer components compared with the Murthy and Swamy´s (see IEEE Transactions on Signal Processing, vol.40, no.5, p.1241-52, 1992) results to integrate two r-bit order statistic filters into an (r+1)-bit order statistic filter; and (3) a scheme for 2-D order statistic filter implementation. In this scheme a large ROM is replaced by very few logic components. In summary, our schemes reduce the chip area of an order statistic filter because much fewer components are used compared with the Murthy and Swamy´s results

Keywords

VLSI; filtering theory; image processing; logic arrays; nonlinear filters; parallel algorithms; parallel architectures; two-dimensional digital filters; 2D order statistic filter; M-array VLSI architecture; algorithms; chip area reduction; image processing applications; logic components; nonlinear filter; parallel algorithm; parallel architecture; Electronic mail; Image processing; Logic; Nonlinear filters; Parallel architectures; Read only memory; Signal processing algorithms; Sorting; Statistics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on

Conference_Location

Atlanta, GA

ISSN

1520-6149

Print_ISBN

0-7803-3192-3

Type

conf

DOI

10.1109/ICASSP.1996.550573

Filename

550573