Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system

This paper presents a strategy for the optimal implementation of algorithms on reconfigurable system based on FPGA technology. The advantage and the originality of our approach are that the implementation obtained combines the execution of algorithm in dynamic reconfiguration realized by temporal hardware partitioning and/or architectural synthesis based on the re-using of the operators. Our approach starts from a CDFG (control-data flow graph) description of an algorithm, and proposes a final implementation based on the computation of the mutual exclusion rate (M.E.R.) parameter for choosing the algorithm parts based on RTR (run time reconfiguration) or AS (architectural synthesis) execution. We also give a general description of the approach. We motivate the effectiveness of this approach by presenting the implementation results of the AES encryption algorithm.