Simulation based cause and effect analysis of cycle time and WIP in semiconductor wafer fabrication

Author

Qi, Chao ; Tang, Tuck Keat ; Sivakumar, Appa Iyer

Author_Institution

Sch. of Mech. & Production Eng., Nanyang Technol. Univ., Singapore

Volume

2

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

1423

Abstract

Semiconductor wafer fabrication is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of part of a wafer fab using ProModel^® software and analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include arrival distribution, batch size, downtime pattern and lot release control. SEMATECH DATASET which has the original actual wafer fab data is used for our analysis.

Keywords

digital simulation; electronic engineering computing; production engineering computing; semiconductor device manufacture; ProModel software; SEMATECH DATASET; WIP level; arrival distribution; batch size; cycle time; downtime pattern; equipment utilization rates; input variables; lot release control; manufacturing processes; semiconductor wafer fabrication; simulation based cause and effect analysis; Analytical models; Cause effect analysis; Electronics industry; Fabrication; Input variables; Manufacturing processes; Production engineering; Semiconductor device modeling; Semiconductor device packaging; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Conference, 2002. Proceedings of the Winter

Print_ISBN

0-7803-7614-5

Type

conf

DOI

10.1109/WSC.2002.1166413

Filename

1166413