Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

Author

Shajaan, Mohammad ; Sorensen, J.A.

Author_Institution

Electron. Inst., Tech. Univ. Denmark, Lyngby, Denmark

Volume

6

fYear

1996

fDate

7-10 May 1996

Firstpage

3268

Abstract

Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach

Keywords

IIR filters; digital signal processing chips; field programmable gate arrays; filtering theory; recursive filters; signal sampling; 15 to 21 MHz; DSP component; FPGA implementation; IIR filters; XC4000; Xilinx field programmable gate array; hardware design; hardware implementation; internal data representation; multiplier free recursive filter architectures; performance; sampling frequencies; time-area efficiency; Band pass filters; Design methodology; Field programmable gate arrays; Finite impulse response filter; Hardware; IIR filters; Optimization methods; Pipeline processing; Poles and zeros; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on

Conference_Location

Atlanta, GA

ISSN

1520-6149

Print_ISBN

0-7803-3192-3

Type

conf

DOI

10.1109/ICASSP.1996.550574

Filename

550574