Rapid RTL-based signal ranking for FPGA prototyping

As the capacity of integrated circuits increases, it is becoming increasingly difficult to ensure that a chip is free of design errors. Designers are increasingly turning to FPGA prototyping platforms to validate their designs much more extensively than is possible using simulation. A key challenge is one of visibility; signals can only be observed if they can be driven to pins of a chip. To enhance visibility during debug, designers regularly instrument their design with on-chip circuitry to record a small subset of signals at-speed for later off-chip analysis. The selection of which signals should be recorded critically affects the effectiveness of this approach. In this paper, we present an algorithm that ranks all signals in a design based on their predicted importance during validation. Compared to previous techniques, which analyze the circuit at the gate level, our algorithm works directly on the parse-tree representation of the circuit, and hence is orders of magnitude faster than these previous techniques. Our algorithm has been implemented as an integral part of Tektronix Certus, a commercial validation suite.