A 42.5 mm/sup 2/ 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability

Author

Kraus, W. ; Lehman, L. ; Wilson, D. ; Yamazaki, T. ; Ohno, C. ; Nagai, E. ; Tamazaki, H. ; Suzuki, H.

Author_Institution

Ramtron Int. Corp., Colorado Springs, CO, USA

fYear

1998

fDate

11-13 June 1998

Firstpage

242

Lastpage

245

Abstract

A 1 Mb ferroelectric random access memory (FRAM(R)) with 15.8 /spl mu/m/sup 2/ cell size and 60 ns read/write times incorporates a one transistor, one capacitor (1T1C) architecture. Data retention reliability is improved by the use of a precharged ferroelectric capacitor reference, an in-pitch ferroelectric capacitor circuit for wordline boosting, and an optimized sensing scheme. Active power is 50 mW @ 5.0 V. PZT capacitors are used with a 0.5 /spl mu/m CMP planarized CMOS process.

Keywords

CMOS memory circuits; ferroelectric capacitors; ferroelectric storage; integrated circuit reliability; random-access storage; 0.5 micron; 1 Mbit; 1T1C architecture; 5.0 V; 50 mW; 60 ns; CMP planarized CMOS process; FRAM; PZT capacitors; active power; cell size; data retention; in-pitch ferroelectric capacitor circuit; nonvolatile ferroelectric memory; one-transistor one-capacitor architecture; optimized sensing scheme; precharged ferroelectric capacitor reference; read/write times; reliability; wordline boosting; Capacitors; Circuits; Electrodes; Ferroelectric materials; Memory architecture; Nonvolatile memory; Polarization; Pulse amplifiers; Radiofrequency identification; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688101

Filename

688101