Power Macromodeling for IP Modules

In this paper, we propose a power macromodeling technique for digital electronic circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed for register transfer level and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.94%. Our model provides accurate power estimation.