• DocumentCode
    2962620
  • Title

    Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method

  • Author

    Yuan Li ; Chow, Peter ; Jiang Jiang ; Minxuan Zhang ; Shaojun Wei

  • Author_Institution
    Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2012
  • fDate
    10-12 Dec. 2012
  • Firstpage
    190
  • Lastpage
    197
  • Abstract
    We present a hardware architecture for efficient implementation of a Gaussian random number generator (GRNG), using the Monty Python method. To maximize the performance/complexity efficiency, an efficient word-length optimization model is proposed to find out both the optimal integer and fractional word-lengths for signals. Experimental results show that our optimized Fixed-Point design achieves a throughput of almost 1 sample-per-cycle and runs as fast as 375.9 MHz on a Xilinx XC6VLX240T FPGA device. This performance is 23.4-fold faster than a dedicated software version running on a 2.67-GHz Intel core i5 processor. It takes 1976 LUTs, 1785 Flip-Flops, 12 BRAMs and 35 DSPs, which is only about 1% of the device as well as a great reduction compared to its corresponding Floating-Point implementations. Furthermore, we develop a framework that is capable of partitioning the Gaussian distribution stream into an arbitrary number of parallel sub-streams. With support from software, this framework can obtain speedup roughly linearly with the number of parallel cores. The quality of the variables produced by our design are verified via the standard Gaussian statistical test suit, the chi-square (X2) test.
  • Keywords
    Gaussian distribution; computational complexity; digital signal processing chips; field programmable gate arrays; fixed point arithmetic; flip-flops; floating point arithmetic; parallel architectures; performance evaluation; random number generation; statistical testing; BRAM; DSP; GRNG; Gaussian distribution; Intel core i5 processor; LUT; Monty Python method; Xilinx XC6VLX240T FPGA device; chi-square test; complexity efficiency maximization; flip-flop; floating-point implementations; frequency 2.67 GHz; hardware architecture; optimal fractional word-lengths; optimal integer word-lengths; optimized fixed-point design; parallel Gaussian random number generation; parallel substreams; performance efficiency maximization; software-hardware framework; standard Gaussian statistical test suit; word-length optimization model; Algorithm design and analysis; Computer architecture; Generators; Hardware; Optimization; Polynomials; Software;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology (FPT), 2012 International Conference on
  • Conference_Location
    Seoul
  • Print_ISBN
    978-1-4673-2846-3
  • Electronic_ISBN
    978-1-4673-2844-9
  • Type

    conf

  • DOI
    10.1109/FPT.2012.6412133
  • Filename
    6412133