Implicit Sampling Analog-to-Digital Converter

A low-temperature superconductor multi-bit implicit-sampling analog-to-digital converter (ADC) architecture is proposed for wide bandwidth RF applications. The architecture selected differs in several respects from both an explicit-sampling Nyquist ADC and an over-sampling ADC. A high-speed axis-crossing detector senses the difference between the input signal and an appropriate reference signal that determines the sampling rate and quantization scheme. The reference signal is chosen to have a peak-to-peak amplitude greater than the expected signal and a fundamental frequency greater than the Nyquist rate for the input. When the reference is a recurring linearly-increasing ramp then the ADC is a linear quantizer. When the reference signal is a sinusoid then the ADC is a companding quantizer and encodes the arcsine of the sample value. Since the times that the samples are taken depend on the value of the samples these variable sample time ADCs are referred to as implicit sampling converters