Title :
A linearized 1.6–5 GHz low noise amplifier using positive feedback in 65 nm CMOS
Author :
Nejdel, Anders ; Törmänen, Markus ; Sjöland, Henrik
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
Abstract :
A 1.6-5 GHz low noise amplifier has been designed and simulated in a 65 nm CMOS process. The linearity is increased by employing positive feedback using transistors biased in the sub-threshold region. Simulations show that mismatches in the circuit can be neutralized by adjusting the bias point of the feedback transistors. The amplifier has a noise figure below 3 dB, a third order intercept point of +10 dBm, and a voltage gain above 23 dB. In order to obtain a flat gain the amplifier uses a resistive load in combination with current bleeding transistors which give a noise cancelling effect. The circuit consumes 4.9 mA from a 1.5 V supply.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; circuit simulation; feedback amplifiers; field effect MMIC; integrated circuit design; integrated circuit noise; linearisation techniques; low noise amplifiers; microwave amplifiers; CMOS process; circuit simulation; current bleeding transistors; feedback transistors; flat amplifier gain; frequency 1.6 GHz to 5 GHz; linearized low noise amplifier design; noise cancelling effect; noise figure; positive feedback amplifier; resistive load; size 65 nm; subthreshold region transistor biasing; third order intercept point; voltage 1.5 V; voltage gain; CMOS integrated circuits; Couplings; Europe; Logic gates; Matched filters; Surface acoustic waves;
Conference_Titel :
NORCHIP, 2011
Conference_Location :
Lund
Print_ISBN :
978-1-4577-0514-4
Electronic_ISBN :
978-1-4577-0515-1
DOI :
10.1109/NORCHP.2011.6126738
