Title :
Variable-correction truncated floating point multipliers
Author :
Wires, Kent E. ; Schulte, Michael J. ; Stine, James E.
Author_Institution :
Dept. of Electr. Eng., Lehigh Univ., Bethlehem, PA, USA
fDate :
Oct. 29 2000-Nov. 1 2000
Abstract :
About half the hardware for floating point multipliers is needed only to guarantee correctly rounded results. For multimedia, graphics, and DSP systems, a significant reduction in area, delay, and power can be achieved by producing results that are not correctly rounded. This paper presents an efficient method for designing variable-correction truncated floating point multipliers that produce results with a maximum error of less than one unit in the last place. With this method, several of the less significant columns of the significand multiplier are eliminated and the rounding logic for floating point multiplication is simplified.
Keywords :
floating point arithmetic; logic circuits; multiplying circuits; normalization logic; rounding logic; significand multiplier; variable-correction truncated floating point multipliers; Delay; Digital signal processing; Floating-point arithmetic; Graphics; H infinity control; Hardware; Power engineering and energy; Power engineering computing; USA Councils; Wires;
Conference_Titel :
Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-6514-3
DOI :
10.1109/ACSSC.2000.911211
