Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL

Timing error detection (TED) microprocessors are able to eliminate large timing margins by operating up to a voltage-frequency point in which intermittent errors occur. The detection of these errors requires an error-detection sequential (EDS) circuit. This paper presents the measurements of an EDS circuit called TEDsc. Using subthreshold source-coupled logic, TEDsc is able to dynamically adapt to system-level requirements. Measurements of TEDsc are presented in terms of a new system-level TED definition. TEDsc is implemented in 65 nm CMOS, has an area of 97.5 μm², and consumes 79 pW (V_dd=250 mV). TEDsc operates at a clock period (T_CLK) of 150 F04 at V_dd=400 mV with a sufficiently large detection window. By decreasing the size of the detection window, TEDsc can operate to at least T_CLK=50 F04.