DocumentCode :
2963148
Title :
Robust Symmetric Multiplication for Programmable Analog VLSI Array Processing
Author :
Domínguez-Matas, C. ; Carmona-Galán, R. ; Sánchez-Fernández, F.J. ; Rodríguez-Vázquez, A.
Author_Institution :
CNM-CSIC, Sevilla
fYear :
2006
fDate :
10-13 Dec. 2006
Firstpage :
1332
Lastpage :
1335
Abstract :
This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.
Keywords :
VLSI; analogue integrated circuits; analogue multipliers; cellular neural nets; image processing; neural chips; operational amplifiers; programmable circuits; CNN; binary weighted current mirrors; cellular neural network; current adder; electrically programmable analog multiplier; linearized OTA-based multiplier; linearized transconductor; programmable analog VLSI array processing; real-time image processing; weight distribution scheme; Adders; Array signal processing; Cellular neural networks; Circuits; Input variables; Linearity; Mirrors; Robustness; Transconductors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location :
Nice
Print_ISBN :
1-4244-0395-2
Electronic_ISBN :
1-4244-0395-2
Type :
conf
DOI :
10.1109/ICECS.2006.379728
Filename :
4263621
Link To Document :
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