Low power programmable frequency divider for IEEE 802.15.4a standard

This paper presents a frequency divider with a programmable division ratio between 208 and 320 intended for the standard IEEE 802.15.4a. The divider is based on high speed, low power, triple modulus prescalers. The wide division range is achieved by cascading these programmable prescalers. Each prescaler includes a phase selector and an ECL D-flip-flop which acts as a divider by 2. The triple operation of the prescaler is achieved by switching between different output phases of the D-flip-flop in the positive direction from 0° to 270° and to the negative direction from 270° to 0°. In addition, a clock of 499.2 MHz with 50% duty cycle is available independent of the selected communication channel. The proposed divider has been evaluated for a SiGe BiCMOS technology and a maximum simulated input frequency of at least 13.5 GHz has been achieved.