Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines

Author

Van Olmen, J. ; List, S. ; Tokei, Zs ; Carbonell, L. ; Brongersma, S.H. ; Volders, H. ; Kunnen, E. ; Heylen, N. ; Ciofi, I. ; Khandelwal, A. ; Gelatos, J. ; Mandrekar, J. Gelatos T ; Boelen, P.

Author_Institution

IMEC, Leuven

fYear

2007

fDate

4-6 June 2007

Firstpage

49

Lastpage

51

Abstract

Two of the most important questions concerning the future of interconnects are 1) how scalable is the damascene process to extremely narrow trenches and 2) what is the resistivity of Cu in these trenches? We attempt to answer both these questions through the generation of high aspect ratio, rectangular cross section trenches as narrow as 20 nm using a novel sacrificial Si FIN process flow. To fill such aggressive geometries, we also explore advanced PVD and ALD barrier and seed processes. We find significant electrical yields for 25 to 35 nm test structures with resistivities as predicted by sidewall scattering models.

Keywords

MOSFET; atomic layer deposition; copper alloys; electrical resistivity; integrated circuit interconnections; integrated circuit metallisation; ALD barrier; Cu; FinFET transistor; advanced PVD process; copper damascene lines; copper resistivity scaling; damascene trenches; metallization process; sacrificial silicon FIN process flow; sidewall scattering models; size 20 nm; size 25 nm to 35 nm; Atherosclerosis; Conductivity; Copper; Filling; FinFETs; Geometry; Organic materials; Scattering; Temperature dependence; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382338

Filename

4263650