Title :
Three dimensional chip stacking using a wafer-to-wafer integration
Author :
Chatterjee, Ritwik ; Fayolle, Murielle ; Leduc, Patrick ; Pozder, Scott ; Jones, Bob ; Acosta, Eddie ; Charlet, Barbara ; Enot, Thierry ; Heitzmann, Michel ; Zussy, Marc ; Roman, Antonio ; Louveau, Olivier ; Maitrejean, Sylvain ; Louis, Didier ; Kernevez,
Author_Institution :
Freescale Semicond., Austin
Abstract :
A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.
Keywords :
dielectric materials; integrated circuit design; integrated circuit interconnections; wafer bonding; wafer-scale integration; backside interconnect formation; deep inter-strata via formation; dielectric wafer bonding; electrical measurements; precise wafer-to-wafer alignment; three dimensional chip stacking; wafer patterning alignment; wafer thinning; wafer-to-wafer integration technology; Dielectric measurements; Electric variables measurement; Integrated circuit interconnections; Integrated circuit technology; Silicon on insulator technology; Size measurement; Stacking; Testing; Throughput; Wafer bonding;
Conference_Titel :
International Interconnect Technology Conference, IEEE 2007
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-1069-X
Electronic_ISBN :
1-4244-1070-3
DOI :
10.1109/IITC.2007.382355
