Optimizing ALD WN Process for 65nm Node CMOS Contact Application

Author

Chen, Y.-C. ; Hung, T.-Y. ; Chang, Y.-L. ; Shieh, K. ; Hsu, C.-L. ; Huang, C. ; Yan, WH ; Ashtiani, K. ; Pisharoty, D. ; Lei, W. ; Chang, S. ; Huang, F. ; Collins, J. ; Tzou, S.F.

Author_Institution

United Microelectron. Corp., Tainan

fYear

2007

fDate

4-6 June 2007

Firstpage

105

Lastpage

107

Abstract

ALD tungsten nitride (WN) becomes attractive for CMOS contact liner/barrier application because of its highly conductive and conformal film properties. Due to the distinct differences in its process nature from the traditional PVD processes, a full optimization from film properties to process integration is necessary for the 65 nm CMOS device fabrication. This paper highlights the issues and shows the approaches to address these issues in implementing the ALD WN process for the CMOS contact application.

Keywords

CMOS logic circuits; atomic layer deposition; electrical contacts; nucleation; tungsten compounds; ALD tungsten nitride process; CMOS contact application; CMOS device fabrication; Logic CMOS device integration; PNL; WN; highly conductive film properties; process integration; pulsed nucleation layer; size 65 nm; Adhesives; Atherosclerosis; CMOS process; Electrodes; Fabrication; Filling; Plugs; Scanning electron microscopy; Testing; Thin film devices;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382361

Filename

4263673