Design and FPGA Implementation of Linear FIR Low-pass Filter Based on Kaiser Window Function

Author

Jinding, Gao ; Yubao, Hou ; Long, Su

Author_Institution

Central South Univ., Changsha, China

Volume

2

fYear

2011

fDate

28-29 March 2011

Firstpage

496

Lastpage

498

Abstract

Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR low-pass filter was implemented on EP2C35F672C8 FPGA. Design efficiency and filter performance has been greatly improved.

Keywords

FIR filters; digital signal processing chips; field programmable gate arrays; low-pass filters; DSP Builder system modeling approach; FPGA implementation; Kaiser window function; cut-off frequency; frequency 100 kHz; frequency 61.71 MHz; frequency domain; linear FIR low-pass filter; real time signal processing; signal waveforms; time domain; Adaptive filters; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Low pass filters; Maximum likelihood detection; DSP Builder; FIR; FPGA; Kaiser window; Low-pass filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Computation Technology and Automation (ICICTA), 2011 International Conference on

Conference_Location

Shenzhen, Guangdong

Print_ISBN

978-1-61284-289-9

Type

conf

DOI

10.1109/ICICTA.2011.408

Filename

5750933