DocumentCode :
2963886
Title :
Assessing the Effect of Die Sealing in Cu/Low-k Structures
Author :
Kearney, Andrew V. ; Vairagar, Anand V. ; Geisler, Holm ; Zschech, Ehrenfried ; Dauskardt, Reinhold H.
Author_Institution :
Stanford Univ., Stanford
fYear :
2007
fDate :
4-6 June 2007
Firstpage :
138
Lastpage :
140
Abstract :
The integration of porous low-k dielectric materials in backend structures in microelectronics has presented numerous processing and reliability challenges, as their porous structure make them mechanically weaker than the fully dense materials they have replaced. Sawing of the wafer into individual die can nucleate cracking along the perimeter which can propagate to reduce device yield and significantly impact the interconnect structure. Die sealing structures have been shown to substantially increase the fracture and damage resistance of the interconnect structure. In this study, we describe fracture mechanics methods using both monotonic and cyclic fatigue loading to assess the effects of die seal structures.
Keywords :
chip scale packaging; copper alloys; fatigue; fracture mechanics; integrated circuit interconnections; integrated circuit reliability; low-k dielectric thin films; porous materials; Cu; backend structures; chip packaging; copper-low-k structures; cyclic fatigue loading; die sealing effect; die sealing structures; fracture mechanics methods; interconnect structure; microelectronics; monotonic fatigue loading; porous low-k dielectric materials; porous structure; wafer dicing; Capacitive sensors; Dielectric materials; Fatigue; Materials reliability; Mechanical factors; Packaging; Seals; Substrates; Testing; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
International Interconnect Technology Conference, IEEE 2007
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-1069-X
Electronic_ISBN :
1-4244-1070-3
Type :
conf
DOI :
10.1109/IITC.2007.382363
Filename :
4263675
Link To Document :
بازگشت