Title :
Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process
Author :
Graf, W. ; Genz, O. ; Kohler, D. ; Prenz, H. ; Schupke, K. ; Laessig, A. ; Bartholomaeus, L.
Author_Institution :
Qimonda Dresden GmbH & Co. OHG, Dresden
Abstract :
A novel self aligned contact integration manufacturing method with oxide spacer is presented. Two main issues of conventional self aligned contacts are solved: high parasitic capacitive coupling through the nitride spacer and the small process window of the SAC etch. Parasitic coupling was reduced by 34 %. For the first time self aligned contacts with oxide spacer are used in DRAM production on 90 and 75 nm. The technology is seen to be extendible to 40 nm and below.
Keywords :
DRAM chips; capacitance; etching; integrated circuit manufacture; integrated circuit testing; nanoelectronics; DRAM production; SAC etching; nitride spacer; oxide spacer; parasitic capacitive coupling; process window; self aligned contact integration manufacturing method; self aligned contact process scaling; size 75 nm; size 90 nm; Atherosclerosis; Capacitance; Etching; Manufacturing processes; Random access memory; Silicon; Space technology; Testing; Tin; Tungsten;
Conference_Titel :
International Interconnect Technology Conference, IEEE 2007
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-1069-X
Electronic_ISBN :
1-4244-1070-3
DOI :
10.1109/IITC.2007.382369
