DocumentCode
2964045
Title
The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks
Author
Sekar, Deepak C. ; Meindl, James D.
Author_Institution
Georgia Inst. of Technol., Georgia
fYear
2007
fDate
4-6 June 2007
Firstpage
123
Lastpage
125
Abstract
This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.
Keywords
integrated circuit design; integrated circuit interconnections; integrated logic circuits; microprocessor chips; microwave integrated circuits; multiprocessor interconnection networks; parallel architectures; chip-level interconnect network design; dual core processor; frequency 3 GHz; multicore architectures; quad core processor; Delay; Frequency; Logic gates; Microprocessors; Optimization methods; Parallel processing; Repeaters; Routing; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
International Interconnect Technology Conference, IEEE 2007
Conference_Location
Burlingame, CA
Print_ISBN
1-4244-1069-X
Electronic_ISBN
1-4244-1070-3
Type
conf
DOI
10.1109/IITC.2007.382371
Filename
4263683
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