A programmable data-path for MPEG-4 and natural hybrid video coding

Author

Faroqui, A.A. ; Okobdzija, V.G.

Author_Institution

Synopsys Inc., Mountain View, CA, USA

Volume

2

fYear

2000

fDate

Oct. 29 2000-Nov. 1 2000

Firstpage

1675

Abstract

A programmable data-path that supports MPEG standards Synthetic & Natural Hybrid video Coding (SNHC) is presented. It can support a maximum of 16 parallel SIMD integer operations and 2 parallel SIMD floating-point operations. Two new instructions were added in order to increase the execution of 3D graphics and SNHC as well as to speed up IDCT, FFT, and other media signal processing algorithms. These operations are implemented by re-using the hardware without significant increase in area and delay. The datapath has been modeled in Verilog using 0.25u CMOS library and synthesized using Synopsys. All operations are single-cycle running at 200 MHz.

Keywords

CMOS integrated circuits; computer graphics; signal processing; standards; video coding; 3D graphics; CMOS library; MPEG-4; Verilog; area; delay; natural hybrid video coding; parallel SIMD floating-point operations; parallel SIMD integer operations; programmable data-path; Delay; Graphics; Hardware design languages; Libraries; MPEG 4 Standard; MPEG standards; Semiconductor device modeling; Signal processing algorithms; Signal synthesis; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-6514-3

Type

conf

DOI

10.1109/ACSSC.2000.911274

Filename

911274