Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

Author

Farooq, Mukta ; Melville, Ian ; Muzzy, Christopher ; McLaughlin, Paul V. ; Hannon, Robert ; Sauter, Wolfgang ; Muncy, Jennifer ; Questad, David ; Carey, Charles ; Cullinan-Scholl, Mary ; McGahay, Vincent ; Angyal, Matthew ; Nye, Henry ; Lane, Michael ; Li

Author_Institution

IBM Microelectron., Hopewell Junction

fYear

2007

fDate

4-6 June 2007

Firstpage

196

Lastpage

198

Abstract

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Keywords

CMOS integrated circuits; chip scale packaging; dielectric devices; integrated circuit interconnections; semiconductor device reliability; stress analysis; C4 interconnections; Sn-Pb; chip package interaction; chip stresses; inter-level dielectrics; low k BEOL CMOS chip; organic package; oxide terminations; reliability stress; size 65 nm; Assembly; CMOS technology; Dielectrics; Environmentally friendly manufacturing techniques; Fatigue; Lead compounds; Life testing; Packaging; Stress; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382388

Filename

4263700