• DocumentCode
    2964416
  • Title

    Challenges for 3D IC integration: bonding quality and thermal management

  • Author

    Leduca, P. ; de Crecy, F. ; Fayolle, M. ; Charlet, B. ; Enot, T. ; Zussy, M. ; Jones, B. ; Barbe, J.-C. ; Kernevez, N. ; Sillon, N. ; Maitrejean, Sylvian ; Louisa, D.

  • Author_Institution
    CEA LETI-MINATEC, Grenoble
  • fYear
    2007
  • fDate
    4-6 June 2007
  • Firstpage
    210
  • Lastpage
    212
  • Abstract
    In this contribution, two main challenges for wafer-to wafer 3D integration are investigated: bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding process considered in this study is direct SiO2/SiO2 hydrophilic bonding. It is shown that, after process optimization, lower than 1.5 mum misalignment was achieved without significant bonding defects. In a second part, a 3D thermal modeling was done to estimate the temperature increase in a two-stratum 3D integration. Local (3D) and global (ID) modeling contribution to the maximum temperature are discussed. It is shown that, thermal resistance due to local 3D effects can be higher than ID thermal resistance. However, thermal effects seem to be manageable.
  • Keywords
    optimisation; silicon compounds; thermal management (packaging); thermal resistance; wafer bonding; SiO2-SiO2; hydrophilic bonding; process optimization; thermal management; thermal resistance; wafer-to wafer two-stratum 3D IC integration; Dielectric substrates; Integrated circuit interconnections; Quality management; Silicon; Stacking; Temperature; Thermal management; Thermal resistance; Three-dimensional integrated circuits; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    International Interconnect Technology Conference, IEEE 2007
  • Conference_Location
    Burlingame, CA
  • Print_ISBN
    1-4244-1069-X
  • Electronic_ISBN
    1-4244-1070-3
  • Type

    conf

  • DOI
    10.1109/IITC.2007.382392
  • Filename
    4263704