Title :
An asynchronous GALS interface with applications
Author_Institution :
Electr. & Comput. Eng. Dept., Boise State Univ., USA
Abstract :
A low-latency asynchronous interface for use in globally-asynchronous locally-synchronous (GALS) integrated circuits is presented. The interface is compact and does not alter the local clocks of the interfaced local clock domains in any way (unlike many existing GALS interfaces). Two applications of the interface to GALS systems are shown. The first is a single-chip shared-memory multiprocessor for generic supercomputing use. The second is an application-specific coprocessor for hardware acceleration of the Smith-Waterman algorithm. This is a bioinformatics algorithm used for sequence alignment (similarity searching) between DNA or amino acid (protein) sequences and sequence databases such as the recently completed human genome database.
Keywords :
CMOS digital integrated circuits; SPICE; biology computing; coprocessors; high level synthesis; reduced instruction set computing; shared memory systems; system buses; system-on-chip; CMOS process; DNA sequences; RISC processor; SPICE; Smith-Waterman algorithm; amino acid sequences; application-specific coprocessor; asynchronous GALS interface; binary tree bus structure; bioinformatics algorithm; clock domain boundaries; clock trees; compact interface; datapath area; generic supercomputing; globally-asynchronous locally-synchronous integrated circuits; hardware acceleration; high-level depiction; human genome database; layout area; low-latency interface; sequence alignment; sequence databases; similarity searching; single-chip shared-memory multiprocessor; synchronous buffer; systems on chip; Acceleration; Amino acids; Bioinformatics; Clocks; Coprocessors; DNA; Databases; Hardware; Proteins; Sequences;
Conference_Titel :
Microelectronics and Electron Devices, 2004 IEEE Workshop on
Print_ISBN :
0-7803-8369-9
DOI :
10.1109/WMED.2004.1297347
