Title :
Metal-insulator-Si (MIS) structure for advanced DRAM cell capacitor
Author :
Zheng, Lingyi Albert ; Ping, ErXuan
Author_Institution :
Res. & Process Dev., Micron Technol. Inc., Boise, ID, USA
Abstract :
The conventional DRAM cell capacitor with silicon-insulator-silicon (SIS) structure limits the scaling of capacitor cell size because the depletion layer of the polycrystalline-Si electrode becomes more severe as the cell dielectrics (ONO) thickness reaches the sub-50 Å region. This paper demonstrates that capacitance can be significantly increased by using a metal-insulator-Si (MIS) structure where the top electrode is metal TiN and the bottom electrode is semi-hemisphere Si grain (HSG). Capacitance can be further enhanced with PH3/NH3 anneal to the HSG. The effects of post high-temperature anneal on the stability of the MIS structure are also discussed.
Keywords :
DRAM chips; MIS capacitors; ammonia; annealing; elemental semiconductors; phosphorus compounds; silicon; thermal stability; titanium compounds; DRAM cell capacitor; HSG; NH3; ONO; PH3; Si; TiN; capacitor cell size scaling; cell dielectric thickness; depletion layer; high-temperature anneal; metal top electrode; metal-insulator-Si structure; semi-hemisphere Si grain bottom electrode; thermal stability; Annealing; Capacitors; Containers; Electrodes; High-K gate dielectrics; Metal-insulator structures; Random access memory; Rough surfaces; Silicon; Tin;
Conference_Titel :
Microelectronics and Electron Devices, 2004 IEEE Workshop on
Print_ISBN :
0-7803-8369-9
DOI :
10.1109/WMED.2004.1297356
