Asymmetric ATM switch modules with imbalanced traffic

This paper analyzes the performance of output channel grouped asymmetric packet switch modules in ATM networks, under geometrically bursty input traffic with input/output traffic imbalance. The switch module considered has n inputs and m outputs. A packet destined for a particular output address (out of g) needs to access only one of the r available physical output ports; m=gr. The motivation for the study of these switch modules is that they are the key building blocks in many large multistage switch architectures. A combination of exact derivation and numerical analysis yields the saturation throughput of input buffered switch modules for a wide range of traffic nonuniformity factors and burstiness. Results show a degradation in the maximum throughput, under input/output imbalance, as the average burst length increases. An interesting observation is that asymmetric switches tend to diminish the throughput advantage of the output-buffered switch module over the input buffered switch module under any traffic nonuniformity and burstiness. Our results also indicate that increasing the number of output ports per output address can significantly improve the switch performance, especially when traffic is highly nonuniform and bursty