Title :
A current mode CMOS multi-layer perceptron chip
Author :
Bo, G.M. ; Caviglia, D.D. ; Valle, M.
Author_Institution :
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
Abstract :
An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the total average power consumption is around 200 mW. This is equivalent to a computational power of about 2.5×109 connections per second. The chip can be employed in a chip-in-the-loop neural architecture
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; feedforward neural nets; multilayer perceptrons; neural chips; neural net architecture; 200 mW; analog VLSI; chip-in-the-loop neural architecture; computational cells; current mode CMOS; feedforward neural net; hidden neurons; multi-layer perceptron chip; neural network integrated circuit; occupied area; power consumption; processing delay; total average power consumption; weak inversion biased MOS transistors; Circuits; Computer architecture; Computer networks; Energy consumption; MOSFETs; Multilayer perceptrons; Neural network hardware; Neural networks; Neurons; Very large scale integration;
Conference_Titel :
Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on
Conference_Location :
Lausanne
Print_ISBN :
0-8186-7373-7
DOI :
10.1109/MNNFS.1996.493778
