• DocumentCode
    296524
  • Title

    A concurrent architecture for 622 Mb/s ATM segmentation and reassembly

  • Author

    Hobson, R.F. ; Wong, P.S.

  • Author_Institution
    Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
  • Volume
    1
  • fYear
    1995
  • fDate
    15-16 May 1995
  • Firstpage
    226
  • Abstract
    The asynchronous transfer mode segmentation and reassembly algorithm for adaptation layer 5 is broken down into concurrent tasks for efficient VLSI implementation
  • Keywords
    VLSI; access protocols; asynchronous transfer mode; digital signal processing chips; parallel architectures; 622 Mbit/s; ATM reassembly; ATM segmentation; VLSI implementation; adaptation layer 5; algorithm; asynchronous transfer mode; concurrent architecture; fiber optic technology; media access control; protocol; Access control; Application software; Asynchronous transfer mode; Computer architecture; Concurrent computing; Cyclic redundancy check; Optical computing; Optical fibers; Payloads; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    WESCANEX 95. Communications, Power, and Computing. Conference Proceedings., IEEE
  • Conference_Location
    Winnipeg, Man.
  • Print_ISBN
    0-7803-2725-X
  • Type

    conf

  • DOI
    10.1109/WESCAN.1995.493975
  • Filename
    493975
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=296524