A test port for interfacing and debugging ARM9 processors implemented in FPGA

Author

Fabay, K.B.F. ; Jardin, J.C.F. ; Jocson, K.J.C. ; Pelayo, B.R.D. ; Alvarez, Anastacia B. ; Madamba, Joy Alinda R. ; Alarcon, Louis P.

Author_Institution

Microelectron. & Microprocessors Lab., Univ. of the Philippines - Diliman, Quezon City, Philippines

fYear

2012

fDate

19-22 Nov. 2012

Firstpage

1

Lastpage

5

Abstract

This paper presents an FPGA implementation of a test port for interfacing and debugging ARM9 processors. The system included a communication interface for debugging the processor, together with the JTAG-based module that granted debugging capability to the selected ARM9 core. Also included was an application software debugger that readily shows the comparison of expected and gathered results from the processor core. The debugging system for the selected ARM9 processor was successfully implemented in a Virtex 5 FPGA development board and was tested using the supported data processing instructions. The latency measured was 0.3 ms per instruction for a baud rate of 4800.

Keywords

electronic engineering computing; field programmable gate arrays; microprocessor chips; program debugging; program testing; ARM9 core; ARM9 processor interfacing; ARM9 processors debugging; FPGA implementation; JTAG-based module; Virtex 5 FPGA development board; application software debugger; communication interface; data processing instructions; debugging capability; debugging system; processor core; test port; Debugging; Field programmable gate arrays; Ports (Computers); Program processors; Registers; Universal Serial Bus; ARM9; Debug; FPGA; JTAG; UART;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2012 - 2012 IEEE Region 10 Conference

Conference_Location

Cebu

ISSN

2159-3442

Print_ISBN

978-1-4673-4823-2

Electronic_ISBN

2159-3442

Type

conf

DOI

10.1109/TENCON.2012.6412304

Filename

6412304