Multi-chip single package 32 bit floating point digital signal processor with built-in 64 K-byte SRAM cache memory

A 32-bit floating-point signal processor IC is integrated with eight 16 K×4-bit SRAM (static random-access memory) chips on a silicon substrate, thus minimizing the parasitic loading of the process buffer and allowing zero-wait-state access to the full 64 Kbyte of memory. The module is rated at 25 MHz up to 125°C and 70 MHz at liquid nitrogen temperature. The assembly is packaged in a standard 133-pin pin-grid-array (PGA) ceramic package identical in size and footprint to the package used for the signal processor IC alone. This packaging approach has significant potential for improving system performance and reducing cost. The signal processing module was designed to demonstrate these improvements. The electrical analysis and design criteria, the physical package, and testing strategies are described