Design and FPGA implementation of orthonormal discrete wavelet transforms

FPGA technology offers the potential for low cost and high performance for certain applications, including image processing. However, the programming model which FPGAs typically present to application developers is prohibitively low level. The purpose of this paper is to present a novel bit-serial architecture based on a time-interleaved structure. To overcome the problem of wait cycles within the structure, a second line of bit adders is provided. This allows the structure to use additional “dummy” cycles to deal with additional bits. The proposed architecture is modular and scalable, which allows a bit-level parameterisation. To assess the effectiveness of the approach the design has been implemented efficiently on the Xilinx 4000 series FPGAs