Modeling of a Buck Converter With a SiC JFET to Predict EMC Conducted Emissions

The reduced switching times of silicon carbide (SiC) components compared to Si components in similar conditions are a great advantage from the point of view of efficiency, but, due to the high dv/dt and di/dt, conducted electromagnetic emissions are increased. Therefore, the availability of a method which can predict these emissions is increasingly necessary. To the best of the authors´ knowledge, a model that can predict differential mode as well as common mode for a converter including sic devices has not yet been published. the novelty of the work presented here is the integration of different modeling approaches to form a circuit model of a SiC-based buck dc-dc converter working in frequency range from 40 Hz to 30 MHz. A modeling approach of the passive parts of the converter is presented. Then, the model obtained is used in simulations to predict the drain-to-source voltage and the drain current for the JFET. Conducted emissions received by the line impedance stabilization network are also computed. Simulation results are compared to measurements for different duty cycles and different gate resistors in the time and frequency domains. A good agreement is obtained. In the frequency domain, in all cases, differences are less than 5 dBμV up to 30 MHz excepted in the JFET source current.