Design issues for early high bit-rate digital subscriber lines

The design and performance of high-bit-rate digital subscriber loop (HDSL) transceivers is examined with the intention of devising systems with signal processing and technology requirements that are not vastly dissimilar to those of basic access transceivers. The topology, line codes, postcursor equalization, precursor equalization, and noise prediction of a simple HDSL transceiver are discussed. A design strategy that would allow early development of an HDSL transceiver to provide 800-kb/s access is explored. A useful benchmark against which the performance versus complexity tradeoff of more sophisticated systems may be assessed is described