Title :
A submicron CMOS two level metal process with planarization techniques
Author :
Fritsch, U. ; Higelin, G. ; Enders, G. ; Müller, W.
Author_Institution :
Siements AG, Munich, West Germany
Abstract :
A double-level meal submicron CMOS process is presented that uses planarization techniques for all possible layers. The authors describe the planarization of poly gates by resist etch back (REB), contact-hole filling with CVD tungsten, intermetal dielectric planarization with a sacrificial layer, and via filling with CVD tungsten. The topography of this CMOS process is given by a field oxide (350 nm), one poly layer (500 nm), and two metal layers (metal 1: 900 nm; metal 2: 1100 nm). Electrical results are given.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; metallisation; tungsten; CVD; W; contact-hole filling; field oxide; planarization; poly gates; resist etch back; sacrificial layer; submicron CMOS two level metal process; topography; via filling; CMOS process; Dielectrics; Etching; Filling; Planarization; Polyimides; Resists; Surfaces; Tin; Tungsten;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14177
