Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies

To design an efficient hardware for ray-triangle intersection, which is the core operation of ray-tracing, we propose a traversal algorithm suitable for hardware design and the associated architecture implementation. In our hardware architecture, multi-threading and folding techniques are used to increase the hardware utilization, and the external memory bandwidth requirement is reduced by multiple cache memories. This design is fabricated by TSMC 0.13 mum technology, and it can achieve better cost-efficiency than pervious works.