DocumentCode
2969232
Title
A formal approach to nonlinear analog circuit verification
Author
Hedrich, L. ; Barke, E.
Author_Institution
Dept. of Electr. Eng., Hannover Univ., Germany
fYear
1995
fDate
5-9 Nov. 1995
Firstpage
123
Lastpage
127
Abstract
This paper presents an approach to nonlinear dynamic analog circuit verification. The input-output behavior of two systems is analyzed to check whether they are functionally similar. The algorithm compares the implicit nonlinear state space descriptions of the two systems on the same or on different levels of abstraction by sampling the state spaces and by building a nonlinear one-to-one mapping of the state spaces. Some examples demonstrate the feasibility of our approach.
Keywords
circuit analysis computing; formal verification; nonlinear network analysis; formal approach; implicit nonlinear state space descriptions; input-output behavior; nonlinear analog circuit verification; nonlinear one-to-one mapping; state spaces; Analog circuits; Analog integrated circuits; Circuit simulation; Differential equations; Digital circuits; Formal verification; Logic circuits; Microelectronics; Sampling methods; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1995.480002
Filename
480002
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