DocumentCode
2969856
Title
Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
Author
Oliveira, Vlademir J S ; Oki, Nobuo
Author_Institution
Univ. Estadual Paulista, Ilha Solteira
fYear
2007
fDate
2-5 Sept. 2007
Firstpage
52
Lastpage
55
Abstract
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mum AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.
Keywords
CMOS analogue integrated circuits; analogue multipliers; current-mode circuits; integrated circuit design; low-power electronics; CMOS analogue integrated circuits; analog CMOS current multiplier; bandwidth 140 MHz; current-mode squarer circuit; frequency 10 MHz; n-well process; size 0.35 mum; voltage 1.5 V; Bandwidth; CMOS process; Circuit topology; Equations; Frequency response; Impedance; Linearity; Low voltage; MOSFETs; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on
Conference_Location
Rabat
Print_ISBN
978-1-4244-1277-8
Electronic_ISBN
978-1-4244-1278-5
Type
conf
DOI
10.1109/DTIS.2007.4449491
Filename
4449491
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