Title :
Digital circuit partition by self-organizing maps: a comparison to classical methods
Author :
Kiziloglu, B. ; Tryba, V. ; Daehn, W.
Author_Institution :
SICAN GmbH, Hannover, Germany
Abstract :
The partitioning of integrated circuits can be executed by using a modified algorithm of the self-organizing map. After a short description of the modified algorithm, an algorithm for the automatic partitioning is explained. The performance of the algorithm is compared to greedy and random algorithms.
Keywords :
circuit CAD; circuit optimisation; digital integrated circuits; graph theory; integrated circuit design; logic partitioning; self-organising feature maps; IC design; digital circuit partitioning; graph partitioning; integrated circuit partitioning; neural nets; optimisation; self-organizing maps; Clustering algorithms; Costs; Digital circuits; Neural networks; Neurons; Packaging; Partitioning algorithms; Pins; Self organizing feature maps; Wires;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.714212
