Developing digital test sequences for through-silicon vias within 3D structures

Through-silicon vias (TSVs) present new, essential elements within 3D stacked Integrated Circuits (IC). Since they connect different layers of 3D stacks, their proper operation is an essential prerequisite for the system function. In this paper a procedure for deriving local digital test sequences for TSVs is presented. The behavior of TSVs including their typical surrounding circuitry is investigated under the impact of assumed faults using fault simulation. Since a purely digital consideration of faulty behavior of TSVs is not sufficient, the TSVs have to be modeled and analyzed at electrical level. The TSVs are embedded by inverters used as drivers at the inputs and buffers at the outputs. All mentioned elements are described at electrical level by spice-like netlists. By an analogue fault simulation tool faults are injected into this electric network model. The simulations of the so modified networks were running in parallel on a compute cluster including the evaluations of the fault effects. The fault simulations are carried out automatically. The test signals needed for fault detection are concatenated to form a digital TSV test sequence.