• DocumentCode
    2970119
  • Title

    Fault-tolerant approaches based on evolvable hardware and using a reconfigurable electronic devices

  • Author

    Keymeulen, Didier ; Stoica, Adrian ; Zebulum, Ricardo ; Jin, Yili ; Duong, Vu

  • Author_Institution
    Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    32
  • Lastpage
    39
  • Abstract
    The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics. The fitness approach defines, in an explicit way, the faults that the component may encounter during its life time and evaluates the average behavior of the individuals. The population approach uses the implicit information of the population statistics accumulated by the genetic algorithm over many generations. The paper presents experiments done using both approaches on a fine-grained CMOS Field Programmable Transistor Array (FPTA) architecture for the synthesis of a fault-tolerant XNOR digital circuit. Experiments show that the evolutionary algorithm is able to find a fault-tolerant design for the XNOR function that can recover functionality when lost due to not a-priori known faults, by finding new circuits configurations that circumvent the faults. Our preliminary experiments show that the population approach designs a fault-tolerant circuit with a better performance and in less computation than the fitness based approach
  • Keywords
    CMOS logic circuits; evolutionary computation; fault tolerance; field programmable gate arrays; genetic algorithms; logic design; CMOS field programmable transistor array; XNOR digital circuit; evolutionary algorithm; evolvable hardware; fault tolerant design; fitness; genetic algorithm; population statistics; reconfigurable electronic device; Algorithm design and analysis; CMOS digital integrated circuits; Circuit faults; Circuit synthesis; Digital circuits; Evolutionary computation; Fault tolerance; Genetic algorithms; Hardware; Statistics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report, 2000 IEEE International
  • Conference_Location
    Lake Tahoe, CA
  • Print_ISBN
    0-7803-6392-2
  • Type

    conf

  • DOI
    10.1109/IRWS.2000.911896
  • Filename
    911896