A novel electrical test to differentiate gate-to-source/drain silicide short from gate oxide short

A novel method that differentiates gate oxide failures from silicide bridging between gate and source/drain is presented. The method can be incorporated into Voltage Ramp Dielectric Breakdown test (VRDB) or as a stand-alone test to detect silicide bridging. It requires the test structure to have gate, source/drain and well terminals. The gate and substrate currents must be monitored during the test at a low gate voltage in accumulation mode. This method uses two criteria, one for the gate current, Ig, and one for the well (substrate) current, Iw. The silicide short was initially simulated by connecting a shunt resistor between the gate and the drain of the device. Actual data are also presented for MOS devices with silicide bridging along with TEM cross-sections