Threshold voltage drift in PMOSFETS due to NBTI and HCI

Threshold voltage drift has become a major process reliability concern for advanced analog and mixed signal technologies. In this paper, PMOSFET threshold voltage drifts (Vt-drifts) due to negative bias temperature instability (NBTI) and hot-carrier injection (HCI) are compared. It is observed that Vt-drifts are much higher under HCI stress condition of Vg=Vd=Vstress than under NBTI stress condition (Vg=Vstress, Vd=0) indicating higher amount of trap generation under HCI stress. However, post-stress anneal experiments showed a higher amount of detrapping in NBTI-stressed devices than in HCI-stressed devices indicating the distinct nature of the traps generated at these two stress conditions. It is also observed that, Vt-drift increases with increase in nitrogen concentration in the gate oxide. For advanced analog and mixed signal applications, process and device reliability limits need to be set up based also on Vt-drift, not only based on traditional methods of Idsat degradation or gate oxide lifetime